By Cheng-Chi Wong, Hsie-Chia Chang
This ebook describes the newest ideas for rapid decoder implementation, specially for 4G and past 4G purposes. The authors show concepts for the layout of high-throughput decoders for destiny telecommunication structures, permitting designers to minimize expense and shorten processing time. insurance contains a proof of VLSI implementation of the rapid decoder, from uncomplicated sensible devices to complicated parallel structure. The authors talk about either structure suggestions and experimental effects, displaying the diversities in area/throughput/performance with recognize to a number of innovations. This publication additionally illustrates faster decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m criteria, which offer a low-complexity yet high-flexibility circuit constitution to help those criteria in a number of parallel modes. in addition, a few strategies that may triumph over the challenge upon the speedup of parallel structure by means of amendment to faster codec are provided right here. in comparison to the normal designs, those equipment may end up in at such a lot 33% achieve in throughput with related functionality and related cost.
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Additional resources for Turbo Decoder Architecture for Beyond-4G Applications
15) Modulo 10;11 11;12 2:7 2:7 270:0 275:2 19:9 19:9 18:1 16:7 74:0 45:2 28:4 35:7 32:2 40:3 92:6 112:3 the cost of these extra registers is also determined by the CMOS technology and memory structure. As either the design objective or available resource varies, it is still possible to use the SISO decoder in Fig. 7 to get the best operating efficiency at relatively lower cost. Chapter 3 Turbo Decoder with Parallel Processing The operating frequency F is the decisive factor in throughput calculation of conventional turbo decoders.
It is still easy to perform these modified equations. With the alternative address generation, the hardware consists primarily of adders and subtractors. The addition of each equation has two operands whose values are both less than N, so the upper bound of their summation is 2N. For those summations greater than N, the modulo operation is carried out easily by subtracting N from them. We can complete all calculations of every recursion step within one cycle. Consequently, the address generator is able to output the interleaving indexes on the fly.
3 Techniques for Efficient Decoding Process 25 The decoding algorithm based on the above three equations is named the Log-MAP algorithm. For the Log-MAP algorithm, a lookup table with high accuracy can lead to the same performance as the MAP algorithm, but it also means the requirement of larger memory. A further simplification can be achieved by completely discarding the lookup table. The correction term will be omitted from the max . 67) This approximation leads to the Max-Log-MAP algorithm that involves only the additions and the max.