By Nauman Khan
This booklet explores the demanding situations and offers most sensible concepts for designing Through-Silicon Vias (TSVs) for 3D built-in circuits. It describes a unique strategy to mitigate TSV-induced noise, the GND Plug, that's more advantageous to others tailored from 2-D planar applied sciences, equivalent to a bottom flooring airplane and conventional substrate contacts. The ebook additionally investigates, within the kind of a comparative learn, the effect of TSV measurement and granularity, spacing of C4 connectors, off-chip strength supply community, shared and devoted TSVs, and coaxial TSVs at the caliber of energy supply in three-D ICs. The authors supply unique most sensible layout practices for designing 3D energy supply networks. considering the fact that TSVs occupy silicon real-estate and influence equipment density, this publication offers 4 iterative algorithms to lessen the variety of TSVs in an influence supply community. not like different current equipment, those algorithms will be utilized in early layout levels while purely sensible block- point behaviors and a ﬂoorplan can be found. eventually, the authors discover using Carbon Nanotubes for strength grid layout as a futuristic substitute to Copper.
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Proposed a partition-based algorithm for assigning modules at the floorplanning level to reuse currents between VDD domains, and to minimize power wasted during circuit operation . In the power integrity analysis area, Huang et al. proposed an analytical physical model of 3-D PDN, accurate within 4% compared to SPICE, to capture the impact of power supply noise . The allocation of decoupling capacitors, in a 3-D IC, has also been investigated [72, 113, 123]. Most of the previous works assume worst case switching currents and utilize overly simplified power grid network models.
A TSV size of 25 μm is therefore used in the following analysis for 3-D PDN. 1 Baseline 3-D Configuration (3-D NOR) This section presents IR and Ldi/dt analysis for the baseline 3-D configuration, described in Sect. 1. We use a TSV size of 25 μm. We run each of the compressed traces for IR and Ldi/dt as described in the Sect. 031 average, and standard deviation. 1. These results form our baseline case, and all other analyses in this chapter are presented in reference to these values. 1, it is clear that the 3-D architecture is not an ideal one because the maximum Ldi/dt voltage droop are considerably higher than their averages.
A small number of TSVs is initially assigned to each node, selected based on the designers’ experiences, or simply with one TSV. During the iterative process, the number of TSVs at the node with the largest voltage violation is incremented. The process repeats until all nodes meet the required noise budget. 1 Reduce Maximum Slack (RMS) We explore in this technique the effectiveness of decreasing the number of TSVs for a node with the largest slack. An initial circuit is generated assuming uniform ni for each grid node.