By Roopak Sinha, Parthasarathi Roop, Samik Basu
This booklet describes an process for designing Systems-on-Chip such that the approach meets targeted mathematical standards. The methodologies awarded allow embedded platforms designers to reuse highbrow estate (IP) blocks from current designs in an effective, trustworthy demeanour, instantly producing right SoCs from a number of, probably mismatching, components.
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Extra resources for Correct-by-Construction Approaches for SoC Design
4. This arrangement is known as a layer. A layer contains a unique decoder, which resolves master requests into slave activation signals. Additionally, if there are multiple masters, an arbiter is included, Master 1 Master 2 Arbiter Slave 1 Address Slave 2 Slave enable signals Decoder Data Bus Address Bus Fig. 4 Single-layer AHB 16 2 The AMBA SOC Platform Master 1 Decoder Master 1 Master 2 Slave 1 Arbiter Address Slave select signals Address Slave 1 enable Slave1 Slave 2 enable Slave 2 Slave 2 Arbiter Master 2 Decoder Data Bus Address Bus Fig.
In the path, ϕ1 is not satisfied in some state before a state satisfying ϕ2 . • In the path, ϕ2 is not satisfied in any state. Based on the above equivalences, there are five key CTL formula equivalences: AXϕ = AGϕ = AFϕ = A(ϕ1 U ϕ2 ) = EFϕ = ¬EX¬ϕ ¬EF¬ϕ ¬EG¬ϕ ¬E(¬ϕ2 U (¬ϕ1 ∧ ¬ϕ2 )) ∧ ¬EG¬ϕ2 E(true U ϕ ) Note that, ¬E(ϕ1 U ϕ2 ) cannot be expressed as AU-CTL formula. This is because ¬E(ϕ1 U ϕ2 ) = A¬(ϕ1 U ϕ2 ) = A( (¬ϕ2 U (¬ϕ1 ∧ ¬ϕ2 )) ∨ G¬ϕ2 ) As universal quantification (in this case A—universal path quantifier) does not distribute over disjunction, it is not possible to express the right-hand side as a valid CTL formula (recall that, valid CTL formula requires pairing of path quantifiers with state quantifier).
Init: The initial state of the IP upon start up. 2. Request: The master has requested for bus access and is waiting for bus access to be granted by the arbiter. 3. Active: Access has been granted, and the write operation has been started. 4. Complete: The write operation has been completed, and the master can relinquish bus access. The control flow within master 1 can be described using transitions between the above states, as shown in Fig. 7a. Starting from the Init state, the IP enters the Request state, and waits there until the arbiter allows bus access.