By Stefanos Kaxiras
Within the previous couple of years, energy dissipation has develop into a big layout constraint, on par with functionality, within the layout of recent computers. while long ago, the first activity of the pc architect used to be to translate advancements in working frequency and transistor count number into functionality, now energy potency has to be taken under consideration at each step of the layout approach. whereas for it slow, architects were winning in providing forty% to 50% annual development in processor functionality, bills that have been formerly pushed aside finally stuck up. the main serious of those bills is the inexorable elevate in strength dissipation and gear density in processors. energy dissipation matters have catalyzed new subject parts in laptop structure, leading to a considerable physique of labor on extra power-efficient architectures. energy dissipation coupled with diminishing functionality earnings, was once additionally the most reason for the swap from single-core to multi-core architectures and a slowdown in frequency elevate. This publication goals to record the most vital architectural ideas that have been invented, proposed, and utilized to lessen either dynamic energy and static energy dissipation in processors and reminiscence hierarchies. an important variety of thoughts were proposed for quite a lot of occasions and this ebook synthesizes these ideas through targeting their universal features.
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Additional info for Computer Architecture Techniques for Power-Efficiency
5) How does the DVFS landscape change when considering parallel applications on multiplecore processors? When considering one, single-threaded application in isolation, one need only consider the possible asynchrony between compute and memory. In other regards, reducing the clock frequency proportionately degrades the performance. In a parallel scenario, however, reducing the clock frequency of one thread may impact other dependent threads that are waiting for a result to be produced. Thus, when considering DVFS for parallel applications, some notion of critical path analysis may be helpful.
A multi-pass “shaker” algorithm tries to distribute slack evenly in the DAG wherever it exists. , one of the 32 frequencies for the Transmeta Crusoe or one of the 320 in the Intel XScale). Since executing each instruction at a different frequency is not practical, the second phase processes the results of the first phase and aims to find a single minimum frequency per interval for each domain. This is done under the constraint that each domain finishes its work with no more than a fixed—externally set—factor of time dilation.
In this work, they reported their power savings in terms of how many fewer mis-speculated instructions were executed when confidence estimators are used. While metrics like “mis-speculation reduction” can be useful and intuitive proxies for reporting some results, their drawback is that they do not offer a common currency by which to compare the power benefits of multiple distinct power-saving opportunities. Furthermore, they do not extend naturally to studies of thermal issues and other power-related problems.